100th : Delay in chip design phase
We have not completed the design yet. We expect a delay of 2 weeks. The delay is caused by spending more time than expected on elements of the chip that are not related to its main function i.e. calculation of hashes. We have to finish the control logic and power regulation. These elements could be simplified if we would assume a standard powering of chips with buck converters. In an effort to reduce the costs of the hardware we plan a daisy chain like power supply. This requires additional dedicated analog logic.
We are still planing the deployment of the mine at the end of June 2013. 
Created on 2013-03-01 19:03:00 by Leszek Rychlewski; Published on 2013-03-01 19:11:29 by koji;